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DSD
2007
IEEE
178views Hardware» more  DSD 2007»
15 years 10 months ago
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
Esra Sahin, Ilker Hamzaoglu
135
Voted
IPPS
2007
IEEE
15 years 10 months ago
A Reconfigurable Load Balancing Architecture for Molecular Dynamics
This paper proposes a novel architecture supporting dynamic load balancing on an FPGA for a Molecular Dynamics algorithm. Load balancing is primarily achieved through the use of s...
Jonathan Phillips, Matthew Areno, Chris Rogers, Ar...
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
15 years 10 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
NOCS
2007
IEEE
15 years 10 months ago
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
Zied Marrakchi, Hayder Mrabet, Christian Masson, H...
FPL
2007
Springer
106views Hardware» more  FPL 2007»
15 years 10 months ago
Monte Carlo Logarithmic Number System for Model Predictive Control
Simple algorithms can be analytically characterized, but such analysis is questionable or even impossible for more complicated algorithms, such as Model Predictive Control (MPC). ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...