1862 search results - page 281 / 373 » FPGA |
161
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FPL
2000
Springer
15 years 8 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
134
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ICCAD
1995
IEEE
15 years 8 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
130
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ARC
2008
Springer
15 years 6 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
130
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...
117
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...