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ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
16 years 1 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow
ICCAD
2004
IEEE
260views Hardware» more  ICCAD 2004»
16 years 1 months ago
On interactions between routing and detailed placement
The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...
Devang Jariwala, John Lillis
124
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ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
16 years 1 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ARC
2010
Springer
387views Hardware» more  ARC 2010»
15 years 11 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
ISQED
2009
IEEE
328views Hardware» more  ISQED 2009»
15 years 11 months ago
VLSI architectures of perceptual based video watermarking for real-time copyright protection
For effective digital rights management (DRM) of multimedia in the framework of embedded systems, both watermarking and cryptography are necessary. In this paper, we present a wat...
Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manis...