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FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
15 years 1 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
FPGA
2006
ACM
139views FPGA» more  FPGA 2006»
15 years 1 months ago
Fast and accurate resource estimation of automatically generated custom DFT IP cores
This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator all...
Peter A. Milder, Mohammad Ahmad, James C. Hoe, Mar...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
15 years 1 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
15 years 1 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
14 years 7 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna