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» Fast simulation of VLSI interconnects
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ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
15 years 8 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
VLSID
2006
IEEE
143views VLSI» more  VLSID 2006»
15 years 5 months ago
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
IPPS
2007
IEEE
15 years 5 months ago
Performance Modelling of Necklace Hypercubes
The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topo...
Sina Meraji, Hamid Sarbazi-Azad, Ahmad Patooghy
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
15 years 5 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
ICMCS
2005
IEEE
133views Multimedia» more  ICMCS 2005»
15 years 4 months ago
Architecture for area-efficient 2-D transform in H.264/AVC
As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevita...
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei ...