160 search results - page 29 / 32 » Fast simulation of VLSI interconnects |
103
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FCCM
2006
IEEE
15 years 5 months ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
108
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ISCA
2012
IEEE
13 years 1 months ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
VLSID
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
VLSID
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
SBCCI
2005
ACM
15 years 4 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...