50 search results - page 6 / 10 » Fault tolerance in cellular automata at high fault rates |
112
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ISCA
2012
IEEE
13 years 1 days ago
2012
IEEE
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
120
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ICDCS
2012
IEEE
13 years 15 hour ago
2012
IEEE
Today’s largest High Performance Computing (HPC) systems exceed one Petaflops (1015 floating point operations per second) and exascale systems are projected within seven years...
CASES
2009
ACM
15 years 4 months ago
2009
ACM
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
WISES
2004
14 years 11 months ago
2004
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
167
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...