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DAC
2004
ACM
15 years 1 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 4 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
EVOW
1999
Springer
15 years 2 months ago
Evolution of Digital Filters Using a Gate Array Model
The traditional paradigm for digital filter design is based on the concept of a linear difference equation with the output response being a weighted sum of signal samples with usua...
Julian F. Miller
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
15 years 3 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose