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GECCO
2009
Springer
108views Optimization» more  GECCO 2009»
15 years 2 months ago
Development of combinational circuits using non-uniform cellular automata: initial results
A non-uniform cellular automata-based model is presented for the evolutionary development of digital circuits at the gate level. The main feature of this model is the modified lo...
Michal Bidlo, Zdenek Vasícek
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
15 years 4 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
IPPS
2006
IEEE
15 years 3 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 3 months ago
Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing
— In this paper, a panoramic camera with speaker oriented face extraction function is proposed. For the face extraction, the Genetic Algorithm(GA) is implemented in a Field Prgra...
Yukinori Nagase, Takahiko Yamamoto, Takao Kawamura...
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
15 years 4 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson