Sciweavers

1563 search results - page 126 / 313
» Flexible instruction processors
Sort
View
ISSS
1999
IEEE
85views Hardware» more  ISSS 1999»
15 years 5 months ago
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
Bart Mesman, Carlos A. Alba Pinto, Koen Van Eijk
103
Voted
BIOCOMP
2006
15 years 2 months ago
Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study
- Aligning specific sequences against other known sequences in a database is a central aspect of bioinformatics. New experimental data being added continuously to these databases n...
Pradeep Nair, Eugene John
105
Voted
ISCAPDCS
2001
15 years 2 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
115
Voted
DCC
2007
IEEE
16 years 20 days ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
101
Voted
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 4 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...