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CODES
2005
IEEE
15 years 5 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ICS
2005
Tsinghua U.
15 years 5 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
ASPLOS
2004
ACM
15 years 5 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
15 years 5 months ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar
HPCA
2000
IEEE
15 years 4 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...