1563 search results - page 90 / 313 » Flexible instruction processors |
101
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DATE
2007
IEEE
15 years 7 months ago
2007
IEEE
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
120
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DAC
1996
ACM
15 years 4 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
ARCS
2006
Springer
15 years 4 months ago
2006
Springer
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
112
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HPCA
2005
IEEE
16 years 1 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
119
Voted
ISCA
1995
IEEE
15 years 4 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...