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POPL
2010
ACM
15 years 10 months ago
Automatically Generating Instruction Selectors Using Declarative Machine Descriptions
Despite years of work on retargetable compilers, creating a good, reliable back end for an optimizing compiler still entails a lot of hard work. Moreover, a critical component of ...
João Dias, Norman Ramsey
130
Voted
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 6 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
129
Voted
CP
2008
Springer
15 years 2 months ago
An Application of Constraint Programming to Superblock Instruction Scheduling
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
Abid M. Malik, Michael Chase, Tyrel Russell, Peter...
114
Voted
ISCAPDCS
2003
15 years 2 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
104
Voted
ASPLOS
1998
ACM
15 years 5 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...