161 search results - page 7 / 33 » Floorplanning with Datapath Optimization |
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
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Voted
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
