Sciweavers

162 search results - page 24 / 33
» Flow Logics for Constraint Based Analysis
Sort
View
FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 1 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
ICCS
2009
Springer
15 years 4 months ago
Access Policy Design Supported by FCA Methods
Role Based Access Control (RBAC) is a methodology for providing users in an IT system specific permissions like write or read to t abstracts from specific users and binds permiss...
Frithjof Dau, Martin Knechtel
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
15 years 2 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
IIWAS
2008
14 years 11 months ago
A model-prover for constrained dynamic conversations
In a service-oriented architecture, systems communicate by exchanging messages. In this work, we propose a formal model based on OCL-constrained UML Class diagrams and a methodolo...
Diletta Cacciagrano, Flavio Corradini, Rosario Cul...
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
15 years 1 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...