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CF
2007
ACM
15 years 3 months ago
Automated generation of layout and control for quantum circuits
We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we in...
Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh...
COR
2006
118views more  COR 2006»
14 years 11 months ago
Simulated annealing heuristics for the dynamic facility layout problem
In today's economy, manufacturing plants must be able to operate efficiently and respond quickly to changes in product mix and demand. Therefore, this paper considers the pro...
Alan R. McKendall Jr., Jin Shang, Saravanan Kuppus...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 6 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ICPR
2008
IEEE
16 years 28 days ago
Incremental machine learning techniques for document layout understanding
In real-world Digital Libraries, Artificial Intelligence techniques are essential for tackling the automatic document processing task with sufficient flexibility. The great variab...
Floriana Esposito, Marenglen Biba, Stefano Ferilli...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
15 years 8 months ago
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Mi...