475 search results - page 1 / 95 » Formal Analysis of Processor Timing Models |
74
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SPIN
2004
Springer
15 years 2 months ago
2004
Springer
Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behavi...
109
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DDECS
2006
IEEE
15 years 1 months ago
2006
IEEE
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
HPCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
JSW
2007
14 years 9 months ago
2007
— UML sequence diagrams focus on the interaction between different classes. For distributed real time transaction processing it is possible to end up with complex sequence diagra...