531 search results - page 5 / 107 » Formal Methods for Networks on Chips |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
VLSID
2003
IEEE
15 years 10 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
FM
2009
Springer
15 years 4 months ago
2009
Springer
This position paper argues that the operational modelling approaches from the formal methods community can be applied fruitfully within the systems biology domain. The results can ...
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...