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158
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DAC
1996
ACM
15 years 7 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
141
Voted
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
16 years 19 days ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
119
Voted
AIMS
2007
Springer
15 years 10 months ago
Harnessing Models for Policy Conflict Analysis
Policy conflict analysis processes based solely on the examination of policy language constructs can not readily discern the semantics associated with the managed system for which ...
Steven Davy, Brendan Jennings
AAAI
1990
15 years 4 months ago
Logical Task Modelling for Man-Machine Dialogue
To design a task-independent dialogue system, we present a task-oriented dialogue analysis in terms of finding the referents of definite descriptions and we show how this analysis...
M. David Sadek
ACL
1989
15 years 4 months ago
A Transfer Model Using a Typed Feature Structure Rewriting System with Inheritance
We propose a model for transfer in machine translation which uses a rewriting system for typed feature structures. The grammar definitions describe transfer relations which are ap...
Rémi Zajac