48 search results - page 3 / 10 » Formal Verification of Diagnosability via Symbolic Model Che... |
JSA
2008
14 years 9 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
EUROMICRO
2000
IEEE
15 years 2 months ago
2000
IEEE
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
ENTCS
2007
14 years 9 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
ISSTA
1998
ACM
15 years 1 months ago
1998
ACM
We present various techniques for improving the time and space efficiency of symbolic model checking for system requirements specified as synchronous finite state machines. We use...
FMCAD
2006
Springer
15 years 1 months ago
2006
Springer
In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent yea...