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» Formal Verification of Digital Systems
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RTCSA
1997
IEEE
15 years 2 months ago
Behavior verification of hybrid real-time requirements by qualitative formalism
Although modern control theories have been successfully applied to solve a variety of problems, they are often mathematically and physically too specific to describe and analyze t...
Jang-Soo Lee, Sung Deok Cha
JCP
2008
116views more  JCP 2008»
14 years 10 months ago
Formal Verification and Visualization of Security Policies
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
Luay A. Wahsheh, Daniel Conte de Leon, Jim Alves-F...
CAV
2010
Springer
286views Hardware» more  CAV 2010»
14 years 10 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
15 years 2 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
97
Voted
JSA
2008
131views more  JSA 2008»
14 years 9 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...