858 search results - page 18 / 172 » Formal Verification of Digital Systems |
90
Voted
CORR
2011
Springer
14 years 5 months ago
2011
Springer
— In recent times, many protocols have been proposed to provide security for various information and communication systems. Such protocols must be tested for their functional cor...
102
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DAC
1996
ACM
15 years 2 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
ISORC
2000
IEEE
15 years 1 months ago
2000
IEEE
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
80
Voted
DATE
2006
IEEE
15 years 4 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
DAC
2009
ACM
15 years 11 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...