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» Formal Verification of Digital Systems
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JUCS
2002
146views more  JUCS 2002»
14 years 10 months ago
A Framework for Semantics of UML Sequence Diagrams in PVS
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...
Demissie B. Aredo
84
Voted
CJ
2004
93views more  CJ 2004»
14 years 10 months ago
An Architecture for Kernel-Level Verification of Executables at Run Time
Digital signatures have been proposed by several researchers as a way of preventing execution of malicious code. In this paper we propose a general architecture for performing the...
Luigi Catuogno, Ivan Visconti
FMCAD
2006
Springer
15 years 2 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
102
Voted
BCS
2008
15 years 11 days ago
Tools for Traceable Security Verification
Dependable systems evolution has been identified by the UK Computing Research Committee (UKCRC) as one of the current grand challenges for computer science. We present work toward...
Jan Jürjens, Yijun Yu, Andreas Bauer 0002
80
Voted
FAC
2008
80views more  FAC 2008»
14 years 11 months ago
Verification of Mondex electronic purses with KIV: from transactions to a security protocol
The Mondex case study about the specification and refinement of an electronic purse as defined in the Oxford Technical Monograph PRG-126 has recently been proposed as a challenge f...
Dominik Haneberg, Gerhard Schellhorn, Holger Grand...