97 search results - page 1 / 20 » Formal verification of behavioral VHDL specifications: a cas... |
208
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FORMATS
2007
Springer
15 years 10 months ago
2007
Springer
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
192
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EUROMICRO
2000
IEEE
15 years 10 months ago
2000
IEEE
In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supp...
187
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ACSC
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper presents a case study for automatic verification using the Communicating Sequential Processes formalism. The case study concerns the Futurebus+ cache coherency standard...
190
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JSA
2008
15 years 5 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...