202 search results - page 2 / 41 » Framework for Fault Analysis and Test Generation in DRAMs |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
DDECS
2007
IEEE
14 years 17 days ago
2007
IEEE
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
ICTAI
2002
IEEE
13 years 11 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...