Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Highly distributed systems such as Grids are used today to the execution of large-scale parallel applications. The behavior analysis of these applications is not trivial. The comp...
Lucas Mello Schnorr, Guillaume Huard, Philippe Oli...
—In this paper we present APOS, a method for dynamically adapting the parameters of IEEE 802.11g to the estimated system state, with the aim of enhancing the quality of a voice c...
—At present wireless devices are able to select their working frequency only to a limited extend although several measurements have shown that the current spectrum regulations ar...
Matthias Wellens, Alexandre de Baynast, Petri M&au...
Abstract— We recast the problem of unconstrained continuous evolutionary optimization as inference in a fixed graphical model. This approach allows us to address several pervasi...
Christopher K. Monson, Kevin D. Seppi, James L. Ca...