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HOST
2008
IEEE
14 years 21 days ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak po...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange...
SEUS
2008
IEEE
14 years 19 days ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic
INTEGRATION
2006
82views more  INTEGRATION 2006»
13 years 6 months ago
On whitespace and stability in physical synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
Saurabh N. Adya, Igor L. Markov, Paul G. Villarrub...
SAC
2008
ACM
13 years 5 months ago
A hybrid software-based self-testing methodology for embedded processor
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ICMCS
2006
IEEE
120views Multimedia» more  ICMCS 2006»
14 years 8 days ago
Video Encoding and Splicing for Tune-in Time Reduction in IP Datacasting (IPDC) Over DVB-H
A novel video encoding and splicing method is proposed which minimizes the tune-in time of “channel zapping”, i.e. changing from one audiovisual service to another, in IPDC ov...
Mehdi Rezaei, Miska M. Hannuksela, Moncef Gabbouj