192 search results - page 10 / 39 » Functional Scan Chain Testing |
97
Voted
TVLSI
2008
14 years 11 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
DAC
2007
ACM
16 years 20 days ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
98
Voted
TCAD
1998
14 years 11 months ago
1998
Conventional scan design imposes considerable area and delay overhead by using larger scan
ip-
ops and additional scan wires without utilizing the functionality of the combinatio...
VTS
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
86
Voted
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...