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CF
2010
ACM
15 years 2 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
87
Voted
ECBS
2006
IEEE
158views Hardware» more  ECBS 2006»
15 years 3 months ago
Automated Translation of C/C++ Models into a Synchronous Formalism
For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system l...
Hamoudi Kalla, Jean-Pierre Talpin, David Berner, L...
PODC
2004
ACM
15 years 3 months ago
Gradient clock synchronization
We introduce the distributed gradient clock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clo...
Rui Fan, Nancy A. Lynch
TMC
2008
107views more  TMC 2008»
14 years 9 months ago
A Mutual Network Synchronization Method for Wireless Ad Hoc and Sensor Networks
Mutual network synchronization is a distributed method in which geographically separated clocks align their times to one another without the need of reference or master clocks. Mut...
Carlos H. Rentel, Thomas Kunz
VLSID
2009
IEEE
87views VLSI» more  VLSID 2009»
15 years 10 months ago
Soft Error Rates with Inertial and Logical Masking
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
Fan Wang, Vishwani D. Agrawal