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ICCAD
2005
IEEE
141views Hardware» more  ICCAD 2005»
16 years 1 months ago
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
Jason Cong, Guoling Han, Zhiru Zhang
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
16 years 1 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
16 years 1 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
15 years 11 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
ICEIS
2009
IEEE
15 years 11 months ago
Invisible Deployment of Integration Processes
Abstract. Due to the changing scope of data management towards the management of heterogeneous and distributed systems and applications, integration processes gain in importance. T...
Matthias Böhm, Dirk Habich, Wolfgang Lehner, ...
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