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90
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CAV
2010
Springer
207views Hardware» more  CAV 2010»
15 years 7 months ago
Petruchio: From Dynamic Networks to Nets
We introduce Petruchio, a tool for computing Petri net translations of dynamic networks. To cater for unbounded architectures beyond the capabilities of existing implementations, t...
Roland Meyer, Tim Strazny
132
Voted
FPGA
2009
ACM
151views FPGA» more  FPGA 2009»
15 years 10 months ago
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and ...
Alastair M. Smith, Steven J. E. Wilton, Joydip Das
176
Voted
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 9 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
165
Voted
STTT
2010
115views more  STTT 2010»
15 years 1 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
122
Voted
CIIA
2009
15 years 4 months ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci