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128
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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
16 years 16 days ago
Platform-based resource binding using a distributed register-file microarchitecture
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
Jason Cong, Yiping Fan, Wei Jiang
208
Voted
SIGCOMM
1995
ACM
15 years 7 months ago
Performance Analysis of MD5
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
Joseph D. Touch
149
Voted
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 6 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
134
Voted
FPL
2004
Springer
110views Hardware» more  FPL 2004»
15 years 9 months ago
Versatile Imaging Architecture Based on a System on Chip
Abstract. In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a F...
Pierre Chalimbaud, François Berry
120
Voted
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
15 years 9 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...