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122
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ICASSP
2008
IEEE
15 years 10 months ago
High-performance scheduling algorithm for partially parallel LDPC decoder
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu
108
Voted
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
15 years 9 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
122
Voted
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
15 years 9 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
133
Voted
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
15 years 5 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
119
Voted
SIGCOMM
2009
ACM
15 years 10 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...