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DAC
2003
ACM
15 years 9 months ago
Symbolic analysis of analog circuits with hard nonlinearity
A new methodology is presented to solve a strongly nonlinear circuit, characterized by Piece-Wise Linear (PWL) functions, symbolically and explicitly in terms of its circuit param...
Alicia Manthe, Zhao Li, C.-J. Richard Shi
163
Voted
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 7 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 5 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
ISLPED
1997
ACM
96views Hardware» more  ISLPED 1997»
15 years 8 months ago
Re-mapping for low power under tight timing constraints
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
133
Voted
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 4 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...