1862 search results - page 89 / 373 » General Architecture for Hardware Implementation of Genetic ... |
141
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ASPDAC
2001
ACM
15 years 7 months ago
2001
ACM
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
111
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ISQED
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
115
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ASAP
1997
IEEE
15 years 7 months ago
1997
IEEE
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
127
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ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...