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2009
ACM
15 years 5 months ago
Enabling software management for multicore caches with a lightweight hardware support
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
ICS
2009
Tsinghua U.
15 years 5 months ago
Cancellation of loads that return zero using zero-value caches
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
Md. Mafijul Islam, Sally A. McKee, Per Stenstr&oum...
ICS
2009
Tsinghua U.
15 years 5 months ago
Dynamic cache clustering for chip multiprocessors
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
TACAS
2009
Springer
128views Algorithms» more  TACAS 2009»
15 years 5 months ago
All-Termination(T)
We introduce the All-Termination(T) problem: given a termination solver, T, and a program (a set of functions), find every set of formal arguments whose consideration is sufficie...
Panagiotis Manolios, Aaron Turon
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
15 years 5 months ago
A formal approach to design space exploration of protocol converters
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
Karin Avnit, Arcot Sowmya