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ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
13 years 10 days ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
ICSR
2009
Springer
15 years 4 months ago
Feature-Driven and Incremental Variability Generalization in Software Product Line
In the lifecycle of a software product line (SPL), incremental generalization is usually required to extend the variability of existing core assets to support the new or changed ap...
Liwei Shen, Xin Peng, Wenyun Zhao
CGO
2009
IEEE
15 years 4 months ago
Computer Generation of General Size Linear Transform Libraries
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
Yevgen Voronenko, Frédéric de Mesmay...
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
15 years 3 months ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...
FMCAD
2009
Springer
15 years 1 months ago
Generalized, efficient array decision procedures
Abstract--The theory of arrays is ubiquitous in the context of software and hardware verification and symbolic analysis. The basic array theory was introduced by McCarthy and allow...
Leonardo Mendonça de Moura, Nikolaj Bj&osla...