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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 28 days ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ICCAD
2002
IEEE
161views Hardware» more  ICCAD 2002»
16 years 28 days ago
Non-tree routing for reliability and yield improvement
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 27 days ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EUROGRAPHICS
2010
Eurographics
15 years 11 months ago
Articulated Billboards for Video-based Rendering
We present a novel representation and rendering method for free-viewpoint video of human characters based on multiple input video streams. The basic idea is to approximate the art...
Marcel Germann, Alexander Hornung, Richard Keiser,...
SI3D
2010
ACM
15 years 11 months ago
Fast capacity constrained Voronoi tessellation
Lloyd relaxation is widely employed to generate point distribution for a variety of applications in computer graphics, computer vision, and image processing. However, Lloyd relaxa...
Hongwei Li, Diego Nehab, Li-Yi Weiy, Pedro V. Sand...
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