305 search results - page 36 / 61 » Geometric programming for circuit optimization |
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
15 years 8 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
114
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ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
110
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ISQED
2008
IEEE
15 years 6 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
ICCD
2008
IEEE
15 years 8 months ago
2008
IEEE
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
FPGA
2010
ACM
15 years 8 months ago
2010
ACM
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...