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BROADNETS
2006
IEEE
15 years 4 months ago
An Energy Efficient and Accurate Slot Synchronization Scheme for Wireless Sensor Networks
Existing slotted channel access schemes in wireless networks assume that slot boundaries at all nodes are synchronized. In practice, relative clock drifts among nodes cause slot mi...
Lillian Dai, Prithwish Basu, Jason Redi
CODES
2006
IEEE
15 years 4 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
15 years 4 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
15 years 4 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
15 years 4 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
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