403 search results - page 69 / 81 » Gradient clock synchronization |
119
Voted
FDL
2004
IEEE
15 years 1 months ago
2004
IEEE
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...
TVLSI
2010
14 years 4 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
70
Voted
DAC
2007
ACM
15 years 10 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...