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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
15 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 1 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
IISWC
2008
IEEE
15 years 4 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
RTCSA
2006
IEEE
15 years 3 months ago
Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE
Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A co...
Soonhoi Ha, Choonseung Lee, Youngmin Yi, Seongnam ...