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TII
2010
146views Education» more  TII 2010»
14 years 7 months ago
A Flexible Design Flow for Software IP Binding in FPGA
Software intellectual property (SWIP) is a critical component of increasingly complex field programmable gate arrays (FPGA)-based system-on-chip (SOC) designs. As a result, develop...
Michael A. Gora, Abhranil Maiti, Patrick Schaumont
104
Voted
IEEEPACT
2009
IEEE
15 years 7 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
FOCS
2004
IEEE
15 years 4 months ago
Edge-Disjoint Paths in Planar Graphs
We study the maximum edge-disjoint paths problem in undirected planar graphs: given a graph G and node pairs (demands) s1t1, s2t2, . . ., sktk, the goal is to maximize the number ...
Chandra Chekuri, Sanjeev Khanna, F. Bruce Shepherd
PLDI
1994
ACM
15 years 4 months ago
The Program Structure Tree: Computing Control Regions in Linear Time
In this paper, we describe the program structure tree (PST), a hierarchical representation of program structure based on single entry single exit (SESE) regions of the control flo...
Richard Johnson, David Pearson, Keshav Pingali
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 4 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha