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» Hardware Architecture of a Parallel Pattern Matching Engine
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FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
15 years 1 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
ACTAC
2002
99views more  ACTAC 2002»
14 years 9 months ago
Recognizing Design Patterns in C++ Programs with the Integration of Columbus and Maisa
A method for recognizing design patterns from C++ programs is presented. The method consists of two separate phases, analysis and reverse engineering of the C++ code, and architec...
Rudolf Ferenc, Juha Gustafsson, Lászl&oacut...
MAM
2007
113views more  MAM 2007»
14 years 9 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
15 years 3 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
75
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AAAI
1990
14 years 10 months ago
The Design of a Marker Passing Architecture for Knowledge Processing
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
Wing Lee, Dan I. Moldovan