Sciweavers

365 search results - page 23 / 73
» Hardware Architecture of a Parallel Pattern Matching Engine
Sort
View
ICPR
2004
IEEE
15 years 10 months ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
IPPS
2007
IEEE
15 years 3 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
AHS
2006
IEEE
145views Hardware» more  AHS 2006»
15 years 1 months ago
The Gannet Service-Based SoC: A Service-level Reconfigurable Architecture
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
Wim Vanderbauwhede
MIDDLEWARE
2004
Springer
15 years 3 months ago
On the benefits of decomposing policy engines into components
In order for middleware systems to be adaptive, their properties and services need to support a wide variety of application-specific policies. However, application developers and ...
Konstantin Beznosov
AFRICACRYPT
2010
Springer
15 years 29 days ago
Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator
Abstract. This article investigates the relevance of the theoretical framework on profiled side-channel attacks presented by F.-X. Standaert et al. at Eurocrypt 2009. The analyses ...
M. Abdelaziz Elaabid, Sylvain Guilley