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DATE
2003
IEEE
105views Hardware» more  DATE 2003»
15 years 3 months ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
15 years 3 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 3 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 2 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
SIGMETRICS
2005
ACM
156views Hardware» more  SIGMETRICS 2005»
15 years 3 months ago
Evaluating the impact of simultaneous multithreading on network servers using real hardware
This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Us...
Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M...