163 search results - page 13 / 33 » Hardware Performance Characterization of Block Cipher Struct... |
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper presents the implementation and experimental characterization of a reconfigurable ΣΔ modulator intended for multi-mode wireless receivers that is capable to perform t...
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
74
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VTS
2008
IEEE
15 years 6 months ago
2008
IEEE
Unlike the top-down photolithographic CMOS VLSI process, cost-effective bulk fabrication of nanodevices calls for a bottom-up approach, generally called self-assembly. Selfassembl...
103
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FPL
2010
Springer
14 years 9 months ago
2010
Springer
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
FSE
1998
Springer
15 years 3 months ago
1998
Springer
ICE is a 64-bit block cipher presented at the Fast Software Encryption Workshop in January 1997. It introduced the concept of a keyed permutation to improve the resistance against ...