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» Hardware Software Co-Design Using Functional Languages
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MTV
2006
IEEE
98views Hardware» more  MTV 2006»
15 years 10 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
ASPLOS
2009
ACM
16 years 5 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ICADL
2005
Springer
114views Education» more  ICADL 2005»
15 years 10 months ago
Scalability of Databases for Digital Libraries
Search engines of main-stream literature digital libraries such as ACM Digital Library, Google Scholar, and PubMed employ file-based systems, and provide users with a basic boolean...
John Chmura, Nattakarn Ratprasartporn, Gultekin &O...
DAC
2007
ACM
16 years 5 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
151
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ASPLOS
2004
ACM
15 years 10 months ago
An ultra low-power processor for sensor networks
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
Virantha N. Ekanayake, Clinton Kelly IV, Rajit Man...