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2008
IEEE
15 years 9 months ago
Intelligent compilers
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
John Cavazos
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 7 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 7 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ICCAD
2000
IEEE
115views Hardware» more  ICCAD 2000»
15 years 6 months ago
Challenges and Opportunities in Broadband and Wireless Communication Designs
Communication designs form the fastest growing segment of the semiconductor market. Both network processors and wireless chipsets have been attracting a great deal of research att...
Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanf...
ICRA
2000
IEEE
91views Robotics» more  ICRA 2000»
15 years 6 months ago
PolyBot: A Modular Reconfigurable Robot
Modular, self-reconfigurable robots show the promise of great versatility, robustness and low cost. This paper presents examples and issues in realizing those promises. PolyBot is...
Mark Yim, David Duff, Kimon Roufas