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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 11 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
CODES
2007
IEEE
16 years 3 days ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 9 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
CLUSTER
2002
IEEE
15 years 10 months ago
Scalable Resource Management in High Performance Computers
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
Eitan Frachtenberg, Fabrizio Petrini, Juan Fern&aa...
CGO
2008
IEEE
16 years 7 days ago
Branch-on-random
We propose a new instruction, branch-on-random, that is like a standard conditional branch, except rather than specifying the condition on which the branch should be taken, it spe...
Edward Lee, Craig B. Zilles